Trace a simplified instruction cycle

A processor runs a program by repeating one cycle: fetch the next instruction from memory, decode it, then execute it. A trace of this cycle shows what the registers hold after each step.

This skill belongs to hardware and processing. It is the foundation for the next lesson on what each register is for, and it links closely to trace tables in algorithm questions.

What happens in each stage?

We use a simplified model with five registers: the program counter (PC), memory address register (MAR), memory data register (MDR), current instruction register (CIR) and accumulator (ACC).

Fetch

1. The address in the PC is copied to the MAR.
2. The PC is increased by 1, so it points at the next instruction.
3. The contents of the memory location in the MAR are copied to the MDR.
4. The contents of the MDR are copied to the CIR.

Decode. The control unit works out what the instruction in the CIR means: which operation, and which address.

Execute. The instruction is carried out. A load copies a value into the ACC, an arithmetic instruction uses the arithmetic logic unit (ALU) and leaves the result in the ACC, and a store copies the ACC to memory.

In pseudocode, the fetch looks like this:

MAR ← PC
PC ← PC + 1
MDR ← Memory[MAR]
CIR ← MDR

Worked example

Memory holds this program and data. LDA 200 loads the value at address 200 into the ACC, ADD 201 adds the value at address 201 to the ACC, STO 202 stores the ACC at address 202, and END stops.

The PC starts at 100. The ACC is empty at the start, shown as a dash.

Check the key values twice. In Execute 2 the ALU adds 7 + 5 = 12. In Execute 3 the value 12 is written to address 202, so location 202 changes from 0 to 12.

Each fetch reads the address the PC held before it increased: 100, 101, 102, 103.

The same cycle in Python, using a dictionary as memory:

memory = {100: "LDA 200", 101: "ADD 201", 102: "STO 202", 103: "END",
          200: 7, 201: 5, 202: 0}
pc = 100
acc = 0
while True:
    mar = pc
    pc = pc + 1
    mdr = memory[mar]
    cir = mdr
    op = cir.split()[0]
    if op == "END":
        break
    address = int(cir.split()[1])
    if op == "LDA":
        acc = memory[address]
    elif op == "ADD":
        acc = acc + memory[address]
    elif op == "STO":
        memory[address] = acc
print(memory[202])   # 12

This is a teaching model, not how a real processor is built, and the safe Python reasoning sandbox lets you run small examples like it.

The mistake to watch for

A frequent slip is to update the PC after the execute stage, or to leave it at the address of the instruction being run.

Mistaken Fetch 1 row: PC 100, MAR 100, MDR LDA 200, CIR LDA 200

The student kept the PC at 100 because “that is where the instruction is”.

The PC is increased during the fetch, so after Fetch 1 it already holds 101. The mistake spreads: every later MAR is then wrong by one, and the whole trace fails. Fix it by writing the PC increase as the second line of every fetch.

Check yourself

1. At the start of a fetch the PC holds 300. Write the values of MAR and PC after the first two steps of the fetch.

2. Which register holds the instruction while the control unit decodes it?

3. An instruction JMP 150 is stored at address 120. State the PC after its fetch and after its execute.

Where this leads next

Now that you can trace the cycle, relate each register to its role and then try the hardware and processing practice set. The restricted pseudocode trace trainer is useful for the same habit of stepping through values.

Some students follow a trace in class but lose the thread alone on a blank page. A teacher in online one-to-one Computer Science tuition can trace with you, one register at a time, until the pattern holds.